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Analytic modeling of tunnel FETs
Update time: 2016-03-18
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Speaker:Prof.Yuan Taur,University of California, San Diego.

Time: 10:00a.m.Wednesday,March 23

Place: A415 SINANO


This talk presents a continuous analytic model for tunnel FETs with a FinFET-type of structure. At the core of the model is a gate-controlled channel potential that satisfies the source and drain boundary conditions. The potential profile is of an exponential nature with the characteristic scale length given by the device thickness. Both the source-to-channel tunneling and source-to-drain tunneling are covered by the model. It has been verified by numerical simulations for a wide range of bandgaps and channel lengths. Also built-in into the model are the short-channel effect, source doping effect, and de-bias of gate voltage by channel charge.


Yuan Taur received the B.S. degree in physics from National Taiwan University, Taipei, Taiwan, and the Ph.D. degree in physics from University of California, Berkeley.

From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. He became a Distinguished Professor in 2014.

Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He has authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book with Dr. Tak Ning of IBM, “Fundamentals of Modern VLSI Devices,” published by Cambridge University Press in 1998. The 2nd edition was published in 2009.

Dr. Yuan Taur received IEEE Electron Devices Society’s J. J. Ebers Award in 2012 “for contributions to the advancement of several generations of CMOS process technologies.” He also received IEEE Electron Devices Society’s Distinguished Service Award in 2014.

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